A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS-Reference-Cited by-同舟云学术

A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS

Published:2015-08-30 Issue:2 Volume:85 Page:299-310
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Chung Hayun,Deniz Zeynep Toprak,Rylyakov Alexander,Bulzacchelli John,Friedman Daniel,Wei Gu-Yeon

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-015-0624-x.pdf

Reference17 articles.

1. Harwood, M. et al. (2007). A 12.5 Gb/s SerDes in 65 nm CMOS using a baud- rate ADC with digital receiver equalization and clock recovery. IEEE International Solid-State Circuits Conference Digest Technical Papers (pp. 436–437).

2. Cao, J. et al. (2009). A 500 mW digitally calibrated AFE in 65 nm CMOS for 10 Gb/s serial links over backplane and multimode fiber. IEEE international solid-state circuits conference digest technical papers (pp. 370–371).

3. Choi, M. et al. (2008). A 6-bit 5-GSample/s Nyquist A/D converter in 65 nm CMOS. IEEE symposium VLSI circuits digest technical papers, pp. 16–17.

4. Park, S., Palaskas, Y., & Flynn, M. (2007). A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 42(9), 1865–1872.

5. Chen, V.-C., & Pileggi, L. (2013). An 8.5 mW 5 GS/s 6b flash ADC with dynamic offset calibration in 32 nm CMOS SOI. IEEE symposium VLSI circuits digest technical papers (pp. 264–265).

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1. A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology;Journal of Electrical Engineering;2017-11-01

2. ADC-Based Backplane Receivers: Motivations, Issues and Future;JSTS:Journal of Semiconductor Technology and Science;2016-06-30