On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique-Reference-Cited by-同舟云学术

On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique

Published:2008-11-26 Issue:2 Volume:58 Page:81-90
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Giustolisi Gianluca,Falconi Christian,D’Amico Arnaldo,Palumbo Gaetano

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-008-9234-1.pdf

Reference20 articles.

1. Leung, K. N., & Mok, P. K. T. (2003). A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE Journal of Solid-State Circuits, 38(10), 1691–1702.

2. Hazucha, P., Karnik, T., Bloechel, B. A., Parson, C., Finan, D., & Borkar, S. (2005). Area-efficient linear regulator with ultra-fast load regulation. IEEE Journal of Solid-State Circuits, 40(4), 933–940.

3. Tantawy, R., & Brauer, E. J. (2004). Performance evaluation of CMOS low drop-out voltage regulators. In Proceedings of the IEEE MWSCAS 2004, Vol. 1, pp. 141–144.

4. Low, A., & Hasler, P. (2004). Basics of floating-gate low-dropout voltage regulators. Proceedings of the IEEE MWSCAS 2000, Aug. 2004.

5. Rincon-Mora, G. A., & Allen, P. E. (1998). A low-voltage, low quiescent current, low drop-out regulator. IEEE Journal of Solid-State Circuits, 33(1), 1265–1272.

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