1. Perrot, M. H., Trott, M. D., & Sodini, C. G. (2002). A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis. IEEE Journal of Solid-State Circuits, 37(8), 1028–1038.
2. Tang, Y., & Ismail, M. (2000). A methodology for fast SPICE simulation of frequency synthesizers. IEEE Circuits and Devices Magazine, 16(4), 10–15.
3. Kundert, K. (2003) Predicting the phase noise and jitter of PLL-based frequency synthesizer. Available from www.designers-guide.com , May.
4. Abhijit, P., & Ramin, S. (1996) Behavioral modeling of a phase locked loop. Southcon/96, pp. 400–404.
5. Rhee, W. (1999). Design of high-performance CMOS charge pumps in phase-locked loops. Proceedings of the IEEE. International Symposium on Circuits and Systems, 99(2), 545–548.