1. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design (2nd ed.). Oxford: Oxford University.
2. Schinkel, D., Mensink, E., Klumperink, E., van Tuijl, E., & Nauta, B. (2007). A double-tail latch-type voltage sense amplifier with 18ps setup+hold time. In: ISSCC2007.
3. Solis, C., & Ducoudray, G. (2010). High resolution low power 0.6m CMOS 40MHz dynamic latch comparator . In: 53rd IEEE international Midwest symposium on circuits and systems (MWSCAS), (pp. 1045–1048).
4. Wicht, B., Nirschl, T., & Schmitt-Landsiedel, D. (2004). Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuits, 39(7), 1148–1158.
5. Goll, B., & Zimmermann, H. (2009). A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(11), 810–814.