Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic-Reference-Cited by-同舟云学术

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

Published:2009-09-16 Issue:3 Volume:63 Page:407-414
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Moon Junho,Song Minkyu,Shin Seungchul,Moon Kyungho,Park Byungha

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-009-9392-9.pdf

Reference16 articles.

1. Van der Plas, G., Chen, A., Geens, P., & Dehaene, W. (1999). A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits, 32, 1708–1718.

2. Cong, Y., Geiger, R. L., & Gray, P. R. (2003). A 1.5 V 14 b 100 MS/s self calibrated DAC. ISSCC Digital Technical Papers, 3(12), 8–129.

3. Van den Bosch, A., Staeyaert, M., & Sansen, W. (1999). SFDR bandwidth limitations for high speed high resolution current steering CMOS D/A converters. Proc. ICECS, 56, 1193–1196.

4. Hwang, S., & Song, M. (2004). A fully integrated current steering 10-b CMOS D/A converter with on-chip terminated resistors. IEICE Transactions on Electronics, E87-C(12), 2179–2185.

5. Manganaro, G., Kwak, S.-U., & Bugeja, A. R. (2004). A dual 10-b 200-MSPS pipelined D/A converter with DLL_based clock synthesizer. IEEE Journal of Solid-State Circuits, 29, 11.

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