Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-017-1012-5/fulltext.html
Reference15 articles.
1. Leung, K. N., & Mok, P. K. (2003). A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE Journal of Solid-State Circuits, 38(10), 1691–1702.
2. Milliken, R. J., Silva-Martinez, J., & Sanchez-Sinencio, E. (2007). Full on-chip CMOS low-dropout voltage regulator. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(9), 1879–1890.
3. Or, P. Y., & Leung, K. N. (2010). An output-capacitorless low-dropout regulator with direct voltage-spike detection. IEEE Journal of Solid-State Circuits, 45(2), 458–466.
4. Guo, J., & Leung, K. N. (2010). A $$6-{\upmu }$$ 6 - μ W chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology. IEEE Journal of Solid-State Circuits, 45(9), 1896–1905.
5. Ho, E. N., & Mok, P. K. (2010). A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(2), 80–84.
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