A 1.8 V low power 5 Gbps PMOS-based LVDS output driver with good return loss performance-Reference-Cited by-同舟云学术

A 1.8 V low power 5 Gbps PMOS-based LVDS output driver with good return loss performance

Published:2013-11-19 Issue:1 Volume:79 Page:1-13
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Marar Hazem W.,Abugharbieh Khaldoon,Al-Tamimi Abdel-Karim

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-013-0224-6.pdf

Reference22 articles.

1. Telecommunications Industry Association. (1996). Electrical characteristics of low voltage differential signaling (LVDS) interface circuits. Arlington: Standard ANSI/TIA/EIA-644 1995.

2. IEEE Standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI), IEEE Std. 1596.3-1996, Jul. 31, 1996.

3. Texas Instruments. (2002). LVDS application and data handbook, Literature Number: SLLD009.

4. National semi conductors. (2008). LVDS owner’s manual, including high-speed CML and signal conditioning (4th ed.).

5. Abugharbieh, K., Krishnan, S., Mohan, J., Devnath, V., & Duzevik, I. (2010). An ultra low-power 10-Gbits/s LVDS output driver. Circuits and Systems, 57(1), 262–269.

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