Dual-loop integer PLL for phase noise reduction
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-022-02072-5.pdf
Reference11 articles.
1. Gardner, F. M. (1980). Charge-Pump Phase-Lock Loops. IEEE Transactions on Communications, 28(11), 1849–1858.
2. Kimball, J. W., & Krein, P. T. (2005). Analysis and design of switched capacitor converters. In Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005. (Vol. 3, pp. 1473–1477).
3. Biswas, D. (2021). Moving average filter for spur reduction in subsampling fractional PLLs. Analog Integrated Circuits and Signal Processing, 109(3), 695–704.
4. Razavi, B. (2012). RF microelectronics (2nd ed.). Pearson Education India.
5. Biswas, D. (2021). Charge Pump with Low Current Mismatch for PLL Applications. In 2021 IEEE international conference on electronics, computing and communication technologies (CONECCT) (pp. 1–4).
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