Detailed implementation of asynchronous circuits on commercial FPGAs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-020-01602-3.pdf
Reference28 articles.
1. Nielsen, L. S., & Sparso, J. (1999). Designing asynchronous circuits for low power: An IFIR filter bank for a digital hearing aid. Proceedings of the IEEE,87(2), 268–281. https://doi.org/10.1109/5.740020.
2. Beigne, E., Vivet, P., Thonnart, Y., Christmann, J. F., & Clermidy, F. (2016). Asynchronous circuit designs for the internet of everything: A methodology for ultralow-power circuits with GALS architecture. IEEE Solid-State Circuits Magazine,8(4), 39–47. https://doi.org/10.1109/mssc.2016.2573864.
3. Pham-Quoc, C., & Dinh-Duc, A. V. (2010). Hazard-free Muller gates for implementing asynchronous circuits on Xilinx FPGA. In IEEE Symposium on Electronic Design, Test & Applications, Ho Chi Minh City, Vietnam, 13–15 Jan. 2010. https://doi.org/10.1109/delta.20https://doi.org/10.40
4. Lavagno, L., Keutzer, K., & Sangiovanni-Vincetelli, A. L. (1995). Synthesis of hazard-free asynchronous circuits with bounded wire delays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,14(1), 61–86. https://doi.org/10.1109/43.363123.
5. UPC/DAC VLSI CAD Group: Petrify. [online]. Retrieved April 26, 2019 from http://www.lsi.upc.edu/~jordicf/petrify
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Efficient Design Flow for Iterative Asynchronous Bundled-Data Circuits on FPGA;2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV);2024-06-06
2. A Modeling Method of Neural Network Activation Function Based on FPGA Multiprocessor;Lecture Notes in Electrical Engineering;2021-10-07
3. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021
4. An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline;IEEE Access;2021
5. A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2020-12-01
1.学者识别学者识别
2.学术分析学术分析
3.人才评估人才评估
"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370
www.globalauthorid.com
TOP
Copyright © 2019-2024 北京同舟云网络信息技术有限公司 京公网安备11010802033243号 京ICP备18003416号-3