A simple circuit technique to relax the feedback timing of ΔΣ ADC for high-speed and high-accuracy applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-017-0993-4/fulltext.html
Reference7 articles.
1. Nam, K., Lee, S. M., Su, D. K., & Wooley, B. A. (2005). A low-voltage low power sigma-delta modulator for broadband analog-to-digital converter. IEEE Journal of Solid-State Circuits, 40(9), 1855–1864.
2. Zanbaghi, R., Saxena, S., Temes, G. C., & Fiez, T. S. (2012). A 75-dB SNDR, 5-MHz bandwidth stage-shard 2-2 MASH ΔΣ modulator dissipating 16 mW power. IEEE Transactions on Circuits Systems Ι: Regular Papers, 59(8), 1614–1625.
3. Silva, J., Moon, U., Steensgaard, J., & Temes, G. C. (2001). Wideband low-distortion ΔΣ ADC topology. Electronics Letters, 37(12), 737–738.
4. Gharbiya, A., & Johns, D. A. (2006). On the implementation of input-feedforward delta-sigma modulator. IEEE Transactions on Circuits Systems II: Express Briefs, 53(6), 453–457.
5. Kanazawa, Y., Fujimoto, Y., Re, P. L., & Miyamoto, M. (2006). A 100-MS/s 4-MHz bandwidth 77.3-dB SNDR ΔΣ ADC with a triple sampling technique. In IEEE Custom Integrated Circuits Conference (CICC), pp. 53–56.
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1. Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications;Electronics;2019-10-09
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