P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-022-01999-z.pdf
Reference11 articles.
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3. Chen, H., Cheng, C., Kahng, A.B., Wang, Q., Mori, M. (2004). Optimal planning for mesh-based power distribution. In: ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), pp. 444–449. DOI https://doi.org/10.1109/ASPDAC.2004.1337616
4. Chowdhury, S. (1989). Optimum design of reliable ic power networks having general graph topologies. In: Proceedings of the 26th ACM/IEEE Design Automation Conference, pp. 787–790. ACM
5. Hussain, S.Z., Rochel, S., Overhauser, D., Saleh, R. (1999). Clock verification in the presence of ir-drop in the power distribution network. In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), pp. 437–440. DOI https://doi.org/10.1109/CICC.1999.777318
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