A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application-Reference-Cited by-同舟云学术

A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application

Published:2015-05-09 Issue:2 Volume:84 Page:261-282
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Kim Hongjin,Lee DongSoo,Lee Juri,Oh SeongJin,Tiwari Honey Durga,Pu YoungGun,Lee Kang-Yoon

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-015-0552-9.pdf

Reference14 articles.

1. IEEE Draft Standard for Information technology. (2010). Wireless medium access control (MAC) and physical layer (PHY) specifications for low-rate wireless personal area networks (WPANs). P802.15.4g/D2.

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3. Staszewski, R. B., & Balsara, P. T. (2006). All-digital frequency synthesizer in deep-submicron CMOS. Hoboken: Wiley.

4. Xu, L., Stadius, K., & Ryynanen, J. (2012). An all-digital PLL frequency synthesizer with an improved phase digitization approach and an optimized frequency calibration technique. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(11), 2481–2494.

5. Chen, J., Rong, L., Jonsson, F., Yang, G., & Zheng, L.-R. (2012). The design of all-digital polar transmitter based on ADPLL and phase synchronized ΔΣmodulator. IEEE Journal of Solid-State Circuits, 47(5), 1154–1164.

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