An efficient and unified 2D-inverse integer cosine transform (IICT) FPGA-hardware implementation for HEVC standard-Reference-Cited by-同舟云学术

An efficient and unified 2D-inverse integer cosine transform (IICT) FPGA-hardware implementation for HEVC standard

Published:2019-06-05 Issue:3 Volume:101 Page:431-440
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Kammoun Ahmed^ORCID,Belghith Fatma,Loukil Hassen,Masmoudi Nouri

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-019-01469-z.pdf

Reference19 articles.

1. ITU-T Recommendation H.265 and ISO/IEC 23008–2 MPEG-H Part 2, High Efficiency Video Coding (HEVC) (2013).

2. Gary, J. S., Woo-Jin, H., & Thomas, W. (2012). Overview of the high efficiency video coding (HEVC) standard. In Circuits and systems for video technology.

3. Wiegand, T., Sullivan, G. J., Bjøntegaard, G., & Luthra, A. (2003). Overview of the H.264/AVC Video Coding Standard. IEEE Transactions on Circuits And Systems for Video Technology, 13(7), 560–576.

4. Seo, Chanwon, & Han, Jongki. (2010). Video coding performance for ierarchical coding block and transform block structures. Korea Society Broading Engineers Magazine, 15(4), 23–34.

5. Kim, I.-K., Min, J., Lee, T., Han, W.-J., & Park, J. H. (2012). Block partitioning structure in the HEVC standard. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1697–1706.

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