A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-018-1222-5/fulltext.html
Reference13 articles.
1. Murmann, B., Nikaeen, P., Connelly, D. J., & Dutton, R. W. (2006). Impact of scaling on analog performance and associated modeling needs. IEEE Transactions on Electron Devices, 53(9), 1.
2. Chen, S. W. M., & Brodersen, R. W. (2006). A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13 $$\mu$$ μ m. IEEE Journal of Solid-State Circuits, 41(12), 2669–2680.
3. Jiang, T., Liu, W., Zhong, F. Y., Zhong, C., Hu, K., & Chiang, P. Y. (2012). A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive approximation ADC with improved feedback delay in 40-nm CMOS. IEEE Journal of Solid-State Circuits, 47, 2444–2453.
4. Liu, C. -C., Chang, S. -J., Huang, G. -Y., & Lin, Y. -Z. (2010). A 10 bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure. Journal of Solid State Circuits, 45(4), 731–740.
5. Kull, L., Toifl, T., Schmatz, M., Francese, P. A., Menolfi, C., Braendli, M., et al. (2013). A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. IEEE Journal of Solid-State Circuits, 48(12), 3049–3058.
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