Feature extraction without learning in an analog spatial pooler memristive-CMOS circuit design of hierarchical temporal memory
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-018-1161-1/fulltext.html
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3. Cui, Y., Ahmad, S., & Hawkins, J. (2017). The HTM spatial pooler: A neocortical algorithm for online sparse distributed coding (p. 085035). bioRxiv
4. Fan, D., Sharad, M., Sengupta, A., & Roy, K. (2016). Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing. IEEE Transactions on Neural Networks and Learning Systems, 27(9), 1907–1919.
5. George, D., & Hawkins, J. (2005). A hierarchical Bayesian model of invariant pattern recognition in the visual cortex. In 2005 IEEE international joint conference on neural networks, IJCNN’05, proceedings (Vol. 3, pp. 1812–1817). IEEE
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