TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-022-02047-6.pdf
Reference20 articles.
1. Meimand, H. M., & Roy, K. (2004). Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style. IEEE Transactions on Circuits & Systems, 51(3), 495–503.
2. Larsson, P., & Svenson, C. (1994). Impact of clock slope on true single-phase clocked (TSPC) CMOS circuit. IEEE Journal of solid-State Circuits, 29(6), 723–726.
3. Radhakrishnan, D. (2001). Low-voltage low-power CMOS full adder. IEE Proceeding of Circuits Devices Systems, 148(1), 19–24.
4. Krambeck, R. H., Charles, M. L., & Law, H.-F.S. (1982). High-speed compact circuits with CMOS. IEEE Journal of Solid-State Circuits, 17(3), 614–619.
5. Birla, S., Mahanti, S., & Singh, N. (2020). Leakage reduction technique for nano-scaled devices. Circuit World, 47, 97–104.
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