Low-power CMOS injection-locked and current-mode logic frequency dividers in a 50 GHz LC cross-coupled oscillator

Author:

Hong Jong-phil,Ann Se-Hyuk,Kim Namsoo

Funder

Chungbuk National University

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference12 articles.

1. Mo, Y., Skafidas, E., Evans, R., & Mareels, I. (2008). A 40 Ghz power efficient static CML frequency divider in 0.13-µm CMOS technology for high speed millimeter-wave wireless systems. In ICCSC 2008 conference (pp. 812–815).

2. Plouchart, J. O., Kim, J., Karam, V., Trzcinski, R., & Gross, J. (2006). Performance variation of a 66 GHz static CML divider in a 90 nm SOI CMOS. In ISSCC Digest of Technical papers (pp. 526–527).

3. Cao, C., & Kenneth, K. O. (2005). A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS. IEEE Microwave and Wireless Components Letters, 15(11), 721–723.

4. Park, J., Ahn, S., Jeong, H., & Kim, N. (2014). High-speed CMOS frequency divider with inductive peaking technique. Transactions on Electrical and Electronics Materials, 15(6), 309–314.

5. Fazeel, H. S., Raghavan, L., Srinivasaraman, C., & Jain, M. (2009). Reduction of current mismatch in PLL charge pump. Proceedings of IEEE International Symposium on ISVLSI, 2009, 7–12.

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