Low-power tri-state buffer in MOS current mode logic

Author:

Gupta Kirti,Pandey Neeta,Gupta Maneesha

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference10 articles.

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A High-Speed MCML Logic Gate and Multiplexer Design in 45 nm CMOS Technology;2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT);2022-12-26

2. Design of MCML Based Logic for Low Power Digital Communication Application;2022 International Conference on Disruptive Technologies for Multi-Disciplinary Research and Applications (CENTCON);2022-12-22

3. Design of Current Mode MOS Logic for Low-Power Digital Applications;Lecture Notes in Electrical Engineering;2021

4. Instant Access Memory Design based on an FPGA;2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS);2020-05

5. Tri-state CML Circuits;Model and Design of Improved Current Mode Logic Gates;2019-11-23

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