A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process-Reference-Cited by-同舟云学术

A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

Published:2010-03-05 Issue:1 Volume:65 Page:33-42
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Zhang M.,Haider M. R.,Islam S. K.,Vijayaraghavan R.,Islam A. B.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-010-9459-7.pdf

Reference19 articles.

1. Best, R. E. (1999). Phase-locked loops design, simulation, and applications (4th ed.). New York: McGraw Hill Professional Publishing.

2. Chen, W. Z., & Wu, J. T. (1999). A 2-V, 1.8-GHz BJT phase-locked loop. IEEE Journal of Solid-State Circuits, 34(6), 784–789.

3. Maxim, A. (2003). A low voltage, 10-2550 MHz, 0.15μm CMOS, process and divider modulus independent PLL using zero-VT MOSFETs’. In Proceedings of the 29th European solid-state circuits conference, pp. 105–108.

4. Shamsi, H., Shoaei, O., Zahabi, A., Koolivand, Y., & Doost, R. (2004). Low power and low voltage considerations in the design of a high frequency clock generator. In Proceedings of IEEE Asia-Pacific conference on circuits and systems, Vol. 2, pp. 933–936.

5. Leung, G. C. T., & Luong, H. C. (2004). A 1-V 5.2-GHz CMOS synthesizer for WLAN applications. IEEE Journal of Solid-State Circuits, 39(11), 1873–1882.

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems;Analog Integrated Circuits and Signal Processing;2014-06-01