Author:
Onabajo Marvin,Silva-Martinez Jose
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference18 articles.
1. Agarwal, K., Hayes, J., & Nassif, S. (2008). Fast characterization of threshold voltage fluctuation in MOS devices. IEEE Transactions on Semiconductor Manufacturing, 21(4), 526–533.
2. Bastos, J., Steyaert, M., Graindourze, B., & Sansen, W. (1996). Matching of MOS transistors with different layout styles. In Proceedings of the IEEE international conference on microelectronic test structures (ICMTS) (pp. 17–18).
3. Cadence Design Systems, Inc. (2003). Recommended Monte Carlo modeling methodology for virtuoso spectre circuit simulator application note, 13-18. Available: http://www.cdnusers.org/community/virtuoso/resources/spectre_mcmodelingAN.pdf .
4. Chang, M. (2007). Foundry future: Challenges in the 21st century. In Digest of technical papers IEEE international solid-state circuits conference (ISSCC) (pp. 18–23).
5. Conti, M., Crippa, P., Orcioni, S., & Turchetti, C. (2002). Layout-based statistical modeling for the prediction of the matching properties of MOS transistors. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 49(5), 680–685.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献