Design and analysis of low-power and area efficient N-bit parallel binary comparator-Reference-Cited by-同舟云学术

Design and analysis of low-power and area efficient N-bit parallel binary comparator

Published:2017-06-09 Issue:2 Volume:92 Page:225-231
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Chua Chang,Kumar R. B. N.,Sireesha B.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/article/10.1007/s10470-017-0996-1/fulltext.html

Reference12 articles.

1. Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital systems testing and testable design. Piscataway, NJ: IEEE Press.

2. Suzuki, H., Kim, C. H., & Roy, K. (2007). Fast tag comparator using diode partitioned domino for 64-bit microprocessors. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(2), 322–328.

3. Texas Instruments. (1999). SN7485 4-bit magnitude comparators. Dallas, TX: Texas Instruments.

4. Guangjie, W., Shimin, S., & Lijiu, J. (1996). New efficient design of digital comparator In 2nd International Conference on ASIC, 1996, (pp. 263–266).

5. Ercegovac, M. D., & Lang, T. (2004). Digital arithmetic. San Mateo, CA: Morgan Kaufmann.

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