1. Adeniran, O. A., & Demosthenous, A. (2005). Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs. Proceedings of the 2005 European Conference on, 2, II/55–II/58, 28 Aug to 2 Sep.
2. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design (pp. 768–775). New York: Oxford University Press.
3. Andersen, T. N., Briskemyr, A., Telstø, F., Bjørnsen, J., Bonnerud, T. E., Hernes, B., et al. (2005). A 97mW 110MS/s 12b pipeline ADC implemented in 0.18/spl mu/m digital CMOS. In Design, automation and test in Europe, 2005, DATE 2005, proceedings (Vol. 3, Issue, 7–11, pp. 219–222).
4. Bult, K., & Buchwald, A. (1997). An Embeded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm². IEEE Journal of Solid-State Circuits, 32(12), 1887–1895.
5. Carnes, J., & Moon, U.-K. (2006). The effect of switch resistance on pipelined ADC MDAC settling time. Circuits and systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE international symposium on 21–24 May 2006 (pp. 5251–5254).