Noise transfer characteristics and design techniques of a frequency synthesizer
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-007-9087-z.pdf
Reference12 articles.
1. Sumi, Y., Obote, S., Narai, K., Tsuda, K., Syoubu, K., & Fukui, Y. (1997). Fast settling PLL frequency synthesizer utilizing the frequency detector method speedup circuit. IEEE Transactions on Consumer Electronics, 43(3), 550–558.
2. Kaenel, V. (1998). A high-speed, low-power clock generator for a microprocessor application. IEEE Journal of Solid-State Circuit, 33, 1634–1639.
3. Rategh, H., Samavati, H., & Lee, T. (2000). A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LNA receiver. IEEE Journal of Solid-State Circuit, 35, 780–787.
4. Craninckx, J. & Steyaert, M. (1998). A fully integrated CMOS DCS-1800 frequency synthesizer. IEEE Journal of Solid-State Circuit, 33, 2054–2065.
5. Meghelli, M., Parker, B., Ainspan, H., & Soyuer, M. (2000). SiGe BiCMOS 3.3 V clock and data recovery circuits for 10Gb/s serial transmission systems. IEEE Journal of Solid-State Circuit, 35, 1992–1995.
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