An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique-Reference-Cited by-同舟云学术

An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique

Published:2016-01-19 Issue:3 Volume:86 Page:407-415
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Kim Daehyeok,Park Sunghyun,Lee Munkyo,Nah Sunphil,Song Minkyu

Funder

Hanwha Thales and the NRF

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-016-0693-5.pdf

Reference29 articles.

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2. Ito, T, et.al. (2010). A 3-GS/s 5-bit 36-mW flash ADC in 65-nm CMOS. IEEE Asian solid-state circuits conference (pp. 67–68).

3. Stepanovic, D. et.al. (2012). A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS. IEEE VLSI symposium (pp. 35–36).

4. Sauerbrey, J., Schmitt-Landsiedel, D., & Thewes, R. (2003). A 0.5-V 1-μW successive approximation ADC. IEEE Journal of Solid-State Circuit, 38, 1261–1265.

5. Wang, J. F., Lin, S. C., & Hsu, J. H. (2003). 12-bit fully differential switched capacitor non-calibrating SA-ADC with one reference voltage. The 14th VLSI design/CAD symposium (pp. 68–73).

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