A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider

Author:

Kennedy Michael Peter,Awan Muhammad Asfandyar,Asghar Malik Summair

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference30 articles.

1. Craninckx, J., & Steyaert, M. (1998). Wireless CMOS frequency synthesizer design. London:Kluwer.

2. Craninckx, J., & Steyaert, M. (1995). A 1.75 GHz/3 V dual-modulus divide-by-128/129 prescaler in 0.7 μm CMOS. In Proceedings of ESSCIRC (pp. 254–257).

3. Pfaff, D., & Huang, Q. (1999). A quarter-micron CMOS 1 GHz VCO/prescaler-set for very low power applications. In IEEE Custom Integrated Circuits Conference Digital Technical Papers (pp.649–652).

4. Huang, Q., & Rogenmoser, R. (1996). Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks. IEEE Journal of Solid-State Circuits, 31, 456–463.

5. Lee, J., & Razavi, B. (2003). A 40 GHz frequency divider in 0.18 μm CMOS technology. In Symposium on VLSI Circuits Digital Technical Papers (pp. 259–262).

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