The influence of key length on the area-time complexity of sorting

Author:

Bilardi G.,Preparata F. P.

Publisher

Springer-Verlag

Reference16 articles.

1. C. D. Thompson, “A Complexity Theory for VLSI,“ Ph.D. Thesis, Dept. of Comp. Science, Carnegie-Mellon Univ.; August 1980.

2. R. P. Brent and H. T. Kung, “The chip complexity of binary arithmetic,“ Journal of the ACM, vol. 28, n. 3, pp. 521–534; July 1981.

3. J. Vuillemin, “A combinatorial limit to the computing power of VLSI circuits,“ IEEE Trans. on Comp. vol. C-32, n. 3, pp. 294–300, March 1983.

4. G. Bilardi and F. P. Preparata, “Square tessellation techniques for area-time lower bounds,“ submitted for publication.

5. G. Bilardi, “The Area-Time Complexity of Sorting,“ Ph.D. Thesis, Univ. of Illinois, 1984.

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Characterization of Associative Operations with Prefix Circuits of Constant Depth and Linear Size;SIAM Journal on Computing;1990-04

2. Area complexity of merging;Lecture Notes in Computer Science;1989

3. Optimal VLSI circuits for sorting;Journal of the ACM;1988-10

4. Area-time tradeoffs for selection;Lecture Notes in Computer Science;1987

5. Area-time lower-bound techniques with applications to sorting;Algorithmica;1986-11

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