An optimal scheduling algorithm for testing interconnect using boundary scan-Reference-Cited by-同舟云学术

An optimal scheduling algorithm for testing interconnect using boundary scan

Published:1991-03 Issue:1 Volume:2 Page:117-130
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Lien Jung-Cheun,Breuer Melvin A.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00134948.pdf

Reference21 articles.

1. IEEE Standard 1149.1?1990, ?IEEE Standard Test Access Port and Boundary-Scan Architecture,? IEEE Standards Board, 345 East 47th Street, New York, NY 10017, May 1989.

2. K.P. Parker, ?The impact of boundary scan on board test,? IEEE Design Test Comput. pp. 18?30, August 1989.

3. C. Maunder and F. Beenker, ?Boundary scan: A framework for structured design-for-test,? Proc. Intern. Test Conf., pp. 714?723, 1987.

4. P. Hansen, ?The impact of boundary-scan on board test strategies,? Proc. ATE&I Conf. East, pp. 35?40, Boston, June 1989.

5. W.H. Kautz, ?Testing for faults in wiring networks,? IEEE Trans. Comput. C-23 (4):358?363, April 1974.

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Parametric and Fault Analysis of Next Generation High Speed Interconnects;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON);2022-11-26

2. Configuring a boundary scan chain for optimal testing of non-scan logic clusters;International Journal of Electronics;2000-03

3. Test program synthesis for modules and chips having boundary scan;Journal of Electronic Testing;1993-05