1. Benedetti, A. and Perona, P., “Bit-width optimisation for configurable DSP’s by multi-interval analysis”, Proc. Signals, Systems and Computers, IEEE, 2000.
2. Bondalapati, K. and Prasanna, V.K., “Dynamic precision management for loop computations on reconfigurable architectures”, Proc. FCCM, IEEE, 1999.
3. Budiu, M. et. al. “BitValue inference: detecting and exploiting narrow bitwidth compilations”, Proc. EuroPar Conf., 2000.
4. Celoxica Limited, http://www.celoxica.com .
5. Constantinides, G.A., Cheung, P.Y.K. and Luk, W., “The multiple wordlength paradigm”, Proc. FCCM, IEEE, 2001.