An Improved Digital FIR Filter Design Using Fast FIR Algorithm and Modified Carry Save Addition
Author:
Publisher
Springer Science and Business Media LLC
Subject
Engineering (miscellaneous)
Link
http://link.springer.com/article/10.1007/s40009-018-0627-0/fulltext.html
Reference14 articles.
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2. Chen PY, Van LD, Khoo IH, Reddy HC, Lin CT (2011) Power-efficient and cost-effective 2-D symmetry filter architectures. IEEE Trans Circuits Syst I: Regul Pap 58(1):112–125
3. Gustafsson O (2007) A difference based adder graph heuristic for multiple constant multiplication problems. In: Proceedings of IEEE International Symposium on Circuits Systems pp 1097–1100
4. Chen KH, Chiueh TD (2006) A low-power digit-based reconfigurable FIR filter. IEEE Trans Circuits Syst II, Exp Briefs 53(8):617–621
5. Mahesh R, Vinod AP (2010) New reconfigurable architectures for implementing filters with low complexity. IEEE Trans Comput Aided Des Integr Circuits Syst 29(2):275–288
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1. A low power transistor level FIR filter implementation using CMOS 45 nm technology;International Journal of Nanotechnology;2023
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