Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study
Author:
Publisher
Springer Science and Business Media LLC
Subject
Engineering (miscellaneous)
Link
http://link.springer.com/content/pdf/10.1007/s40009-019-00830-0.pdf
Reference11 articles.
1. Khemka V, Zhu R, Bose A, Roggenbauer T (2007) Optimization and elimination of parasitic latchup in advanced smart-power technologies. IEEE Trans Dev Mater Reliab 7(1):69–73
2. Lo Conte F, Sallese JM, Pastre M, Krummenacher F, Kayal M (2010) Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates. IEEE Trans Electron Dev 57(1):263–272
3. Stefanucci C, Buccella P, Kayal M, Sallese JM (2015) Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs. Solid State Electron 105:21–29
4. Chan WWT, Sin JKO, Wong SS (1998) A novel crosstalk isolation structure for bulk CMOS power IC’s. IEEE Trans Electron Dev 45(7):1580–1586
5. Gupta S, Beckman JC, Kosier SL (2001) Unbiased guard ring for latchup-resistant, junction-isolated smart-power ICs. In: IEEE Proc BCTM, pp 188–191
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