Data Layout Optimization for Portable Performance-Reference-Cited by-同舟云学术

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Data Layout Optimization for Portable Performance

Published:2015 Issue: Volume: Page:250-262
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Sharma Kamal,Karlin Ian,Keasler Jeff,McGraw James R.,Sarkar Vivek

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-662-48096-0_20

Reference20 articles.

1. AMD64 Architecture Programmer’s Manual Volume 2

2. ASC Sequoia Benchmark. https://asc.llnl.gov/sequoia/benchmarks/

3. Extended TALC Infrastructure. https://github.com/rose-compiler/edg4x-rose/tree/master/projects/TALCDataLayout

4. ROSE Compiler Infrastructure. http://rosecompiler.org/

5. Hydrodynamics Challenge Problem. Technical report LLNL-TR-490254, LLNL, July 2011. https://computation.llnl.gov/casc/ShockHydro

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1. ALT: Breaking the Wall between Data Layout and Loop Optimizations for Deep Learning Compilation;Proceedings of the Eighteenth European Conference on Computer Systems;2023-05-08

2. An Affine Scheduling Framework for Integrating Data Layout and Loop Transformations;Languages and Compilers for Parallel Computing;2022

3. Reshape your layouts, not your programs: A safe language extension for better cache locality;Science of Computer Programming;2020-10

4. Locality optimized unstructured mesh algorithms on GPUs;Journal of Parallel and Distributed Computing;2019-12

5. Investigating Data Layout Transformations in Chapel;2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2018-05

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