FPGA Based Low-Latency Market Data Feed Handler
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-662-45815-0_7
Reference10 articles.
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3. Leber, C., Geib, B., Litz, H.: High frequency trading acceleration using FPGAs. In: 2011 International Conference on Field Programmable Logic and Applications (FPL). IEEE (2011)
4. Pasetto, D., et al.: Ultra low latency market data feed on IBM PowerENTM. Computer Science-Research and Development 26(3-4), 307–315 (2011)
5. Morris, G.W., Thomas, D.B., Luk, W.: FPGA accelerated low-latency market data feed processing. In: 17th IEEE Symposium on High Performance Interconnects, HOTI 2009. IEEE (2009)
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1. A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency;Journal of Signal Processing Systems;2023-04
2. An Accelerator for Decoding Market Data Based on FPGA;Journal of Circuits, Systems and Computers;2019-02-24
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