1. Barber MR.. “Fundamental timing problems in testing MOS VLSI on modern ATE. IEEE Design and Test, (1984)8, pp. 90–97.
2. Birolini A., “Moglichkeiten und Grenzen der Qualifikation, Prüfung und Vorbehandlung integrierter Schaltungen”. QZ, 27(1982)11, pp. 321–326; “Prüfung und Vorbehandlung von Bauelementen und bestückten Leiterplatten”. VDI/VDE Fachtag, Karlsruhe; 1984, VD! Bericht Nr. 519, pp. 49–61; -, Büchel W., and Heavner D., “Test and screening strategies for large memories”. 1st European Test Conf., Paris: 1989, pp. 276–283; “Neue Ergebnisse aus der Qualifikation grosser Halbleiterspeicher”. me, 7(1993) 2, pp. 98–102.
3. Boccaletti G., Borr i F., D’Epinosa G., Fioravanti G., and Ghio E., “Accelerated Tests”. pp. 361–399 in [3.73].
4. Brambilla P., Canali C., Fantini F., Magistrali F., and Mattana G., “Reliability evaluation of plastic-packaged devices for long life applications by THB test”. Microel. and Rel., 26(1986)2, pp. 365–384.
5. Crook DL., “Evolution in VLSI reliability engineering”. hit. Rel. Phys. Symp. (IRPS), 1990, pp. 2–11.