A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS-Reference-Cited by-同舟云学术

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A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS

Published:2024-07-17 Issue:8 Volume:67 Page:
ISSN:1674-733X
Container-title:Science China Information Sciences
language:en
Short-container-title:Sci. China Inf. Sci.

Author:

Liu Shubin,Han Chenxi,Zhao Xiaoteng,Zhang Yuhao,Li Shixin,Liang Hongzhi,Yang Lihong,Zhu Zhangming

Publisher

Springer Science and Business Media LLC

Link

https://link.springer.com/content/pdf/10.1007/s11432-024-4072-9.pdf

Reference2 articles.

1. Peng P J, Chen Y T, Lai S T, et al. A 112-Gb/s PAM-4 voltage-mode transmitter with four-tap two-step FFE and automatic phase alignment techniques in 40-nm CMOS. IEEE J Solid-State Circ, 2021, 56: 2123–2131

2. Kim J, Kundu S, Balankutty A, et al. A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET. IEEE J Solid-State Circ, 2022, 57: 6–20

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