Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

Author:

Lu Guangyi,Wang Yuan,Zhang Lizhong,Cao Jian,Zhang Xing

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference24 articles.

1. Amerasekera A, Duvvury C, Anderson W, et al. ESD in Silicon Integrated Circuits. 2nd ed. Chichester: John Wiley & Sons, Ltd, 2002

2. Ker M D. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans Electron Devices, 1999, 46: 173–183

3. Smith J, Cline R, Boselli G. A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, 2003. 1–9

4. Sarbishaei H, Semenov O. A transient power supply ESD clamp with CMOS thyristor delay element. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Anaheim, 2007. 395–402

5. Ker M D, Yen C C. Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test. IEEE J Solid-State Circ, 2008, 43: 2533–2545

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1. Modeling Study of Power-On and Power-Off System-Level Electrostatic Discharge Protection;IEEE Transactions on Electromagnetic Compatibility;2021-08

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