Challenges of 22 nm and beyond CMOS technology

Author:

Huang Ru,Wu HanMing,Kang JinFeng,Xiao DeYuan,Shi XueLong,An Xia,Tian Yu,Wang RunSheng,Zhang LiangLiang,Zhang Xing,Wang YangYuan

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference185 articles.

1. Haran B S, Kumar A, Adam L, et al. 22 nm technology compatible fully functional 0.1 μm 26T-SRAM cell. In: IEDM Tech Dig, 2008. 625–628

2. The International Technology Roadmap for Semiconductors (ITRS) Roadmap. ITRS Roadmap 2007/2008, http://public.itrs.net/

3. Mimotogi S, Satake M, Kitamura Y, et al. Pattering strategy and performance of 1.3 NA tool for 32 nm node lithography. In: Proc of SPIE, San Jose, 2008. 6924: 69240M01–69240M09

4. Lee S S, Wu C H, Huang Y F, et al. Manufacturing implementation of 32 nm SRAM using ArF immersion with RET. In: Proc of SPIE, San Jose, 2008. 6924: 69242X01–69242X10

5. Lin B J. Marching of the microlithography horses: electron, ion, and photon: Past, present, and future. In: Proc of SPIE, San Jose, 2007. 6520: 65200201–65200218

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