Applications of Hierarchical Verification in Model Checking
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/3-540-44798-9_3
Reference18 articles.
1. M. D. Aagaard, R. B. Jones, K. R. Kohatsu, R. Kaivola, and C.-J. H. Seger. Formal verification of iterative algorithms in microprocessors. In DAC, June 2000.
2. M. D. Aagaard, R. B. Jones, and C.-J. H. Seger. Formal verification using parametric representations of Boolean constraints. In DAC, July 1999. (Short paper).
3. M. D. Aagaard, R. B. Jones, and C.-J. H. Seger. Lifted-fl: A pragmatic implementation of combined model checking and theorem proving. In L. Thery, editor, Theorem Proving in Higher Order Logics, pages 323–340. Springer Verlag; New York, Sept. 1999.
4. A. Camilleri. A hybrid approach to verifying liveness in a symmetric multi-processor. In E. L. Gunter and A. Felty, editors, Theorem Proving in Higher Order Logics, pages 49–68. Springer Verlag; New York, Sept. 1997.
5. Y.-A. Chen and R. Bryant. Verification of floating-point adders. In A. J. Hu and M. Y Vardi, editors, CAV, pages 488–499, July 1998.
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