1. A. Ailamaki, D. Dewitt, M. Hill, and D. Wood. Dbms on modern processors: Where does time go? Proc. of the 25th Int. Conf. on Very Large Data Bases, 1999.
2. L. Barroso, K. Gharachorloo, and E. Bugnion. Memory system characterization of commercial workloads. Proc. of the 25th Intl. Symp. on Comp. Architecture, 1998
3. L. Barroso, K. Gharachorloo, A. Nowatzyk, and B. Verghese. Impact of chip-level integration on performance of oltp workloads. Proc. of the 6th Intl. Conf. on High Performance Comp. Architecture, January 2000.
4. D. Burger, T. M. Austin, and S. Bennett. Evaluating future microprocessors: The simplescalar tool set. Technical Report TR-1308, Comp. Sciences Dept., Univ. of Wisconsin-Madison, 1996.
5. T. Conte, K. Menezes, P. Mills, and B. Patell. Optimization of instruction fetch mechanism for high issue rates. Proc. of the 22th Intl. Symp. on Comp. Architecture, pages 333–344, June 1995.