A synthesis of two approaches for verifying finite state concurrent systems-Reference-Cited by-同舟云学术

A synthesis of two approaches for verifying finite state concurrent systems

Published:1989 Issue: Volume: Page:81-90
ISSN:0302-9743
Container-title:Logic at Botik '89
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Author:

Clarke E. M.,Grumberg O.,Kurshan R. P.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-51237-3_7.pdf

Reference22 articles.

1. S. Aggarwal, R. P. Kurshan, and K. K. Sabnani. A Calculus for Protocol Specification and Validation. In Protocol Specification, Testing and Verification, North-Holland, 1983, pp. 19–34.

2. B. Alpern and F. Schneider. Verifying Temporal Properties without using Temporal Logic. Tech. Rept. 85-723, Cornell University Computer Science Department, December, 1985.

3. M. Ben-Ari, Z. Manna, A. Pneuli. "The Temporal Logic of Branching Time". Acta Informatica, 20 (1983), 207–226.

4. M. C. Browne. An Improved Algorithm for the Automatic Verification of Finite State Systems using Temporal Logic. Proceedings of the 1986 Conference on Logic in Computer Science., Cambridge, Massachusetts, June, 1986, pp. 260–267.

5. M. Browne, E. Clarke, D. Dill, B. Mishra. "Automatic Verification of Sequential Circuits using Temporal Logic". IEEE Transactions on Computers C-35, 12 (December 1986).

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