Strategies for a massively parallel implementation of simulated annealing-Reference-Cited by-同舟云学术

Strategies for a massively parallel implementation of simulated annealing

Published:1989 Issue: Volume: Page:273-287
ISSN:0302-9743
Container-title:PARLE '89 Parallel Architectures and Languages Europe
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Author:

Baiardi F.,Orlando S.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-51285-3_46.pdf

Reference8 articles.

1. E.H.L.Aart, J.H.M.Korst, "Bolzmann Machines and Their Applications", Proc. of PARLE 87, LCNS 258, 259, 1987.

2. V.Ansade, R.Cornu-Emieux, B.Faure, G.Mazare, P.Objois, "Algorithms dedicated to a network of asyncronous cells", in Parallel Algorithms & Architecture, North-Holland, 1986.

3. F.Darema, S.Kirpatrick, V.A.Norton, "Parallel algorithms for chip placement by simulated annealing", IBM Jour. of Res. and Develop., vol. 31, no.3, May 87.

4. J.G.Donnet, D.R.Skillicorn, "Code partitioning by Simulated Annealing", Proc. Int. Conf. on Parallel Processing and Applications, pp. 303–308, L'Aquila, Italy, September 1987.

5. T.C.Hu, E.S.Ku, "Theory and concepts of circuit layout", in VLSI Circuit Layout: Theory and Design, IEEE PRESS, 3–17, 1985.

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