A unified signal transition graph model for asynchronous control circuit synthesis-Reference-Cited by-同舟云学术

A unified signal transition graph model for asynchronous control circuit synthesis

Published:1996-11 Issue:3 Volume:9 Page:139-188
ISSN:0925-9856
Container-title:Formal Methods in System Design
language:en
Short-container-title:Form Method Syst Des

Author:

Yakovlev Alexandre,Lavagno Luciano,Sangiovanni-Vincentelli Alberto

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/BF00122081.pdf

Reference43 articles.

1. P.A. Beerel and T.H.-Y. Meng, ?Gate-level synthesis of speed-independent asynchronous control circuits?, in Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 1992.

2. E. Best, ?Structural theory of Petri nets: The free-choice hiatus?, Lecture Notes in Computer Science, Vol. 254, pp. 168?206, 1987.

3. E. Best and K. Voss, ?Free choice systems have home states?, Acta Informatica, Vol. 21, pp. 89?100, 1984.

4. J.A. Brzozowski and C.-J. Seger, ?Advances in asynchronous circuit theory-Part I: Gate and unbounded inertial delay models?, Bulletin of the European Association of Theoretical Computer Science, Oct. 1990.

5. S. Burns and A. Martin, ?A synthesis method for self-timed VLSI circuits?, in Proceedings of the International Conference on Computer Design, 1987.

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