1. D. Balderes and M. White, “Packaging Effects on CPU Perfor- mance of Large Commercial Processors,” Proceedings of the 35th Electronic Components Conference, pp. 351–356, 1985.
2. H. B. Bakoglu and J. D. Meindl, “A System Level Circuit Model for Multi-and Single-Chip CPU’s,” Proceedings of the IEEE International Solid State Circuits Conference, pp. 308–309, 1987.
3. C. A. Neugebauer and R. O. Carlson, Comparison of Wafer Scale Integration with VLSI Packaging Approaches, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. CHMT-10, no. 2, pp. 184–189, June, 1987.
4. J. P. Krusius and W. E. Pence, “Analysis of Materials and Structure Tradeoffs in Thin and Thick Film Multi-Chip Packages,” Proceedings of the Electronic Components Conference, pp. 641–646, 1989.
5. V. K. Nagesh, D. Miller, and L. Moresco, “A Comparative Study of Interconnect Technologies,” Proceedings of the International Electronic Packaging Symposium (IEPS), pp. 433–443, 1989.