Publisher
Springer Science and Business Media LLC
Subject
General Physics and Astronomy
Reference13 articles.
1. S-H Lo, D A Buchanan and Y Taur, IBM J. Res. Develop. 43(3), 327 (1999)
2. T Ghani, K Mistry, P Packan, S Thompson, M Stettler, S Tyagi and M Bohr, Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors, in: 2000 Symposium on VLSI Technology, Digest of Technical Papers (Cat. No.00CH37104)
3. H-S P Wong, Y Taur and D J Frank, Microelectron. Rel. 38(9), 1447 (1998)
4. R Jhaveri, V Nagavarapu and J C S Woo, IEEE Trans. Electron Dev. 58(1), 80 (2011)
5. R K Sharma, R Gupta, M Gupta and R S Gupta, IEEE Trans. Electron Dev. 56(6), 1284 (2009)
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