Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays

Author:

Gaj Kris,Chodowiec Pawel

Publisher

Springer Berlin Heidelberg

Reference12 articles.

1. “Advanced Encryption Standard Development Effort,” http://www.nist.gov/aes .

2. Third Advanced Encryption Standard (AES) Candidate Conference, New York, April 13–14, 2000, http://csrc.nist.gov/encryption/aes/round2/conf3/aes3conf.htm .

3. J. Nechvatal, E. Barker, L. Bassham, W. Burr, M. Dworkin, J. Foti, and E. Roback, “Report on the Development of the Advanced Encryption Standard (AES),” available at [1].

4. A. J. Elbirt, W. Yip, B. Chetwynd, C. Paar, “An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists,” in [2].

5. A. Dandalis, V. K. Prasanna, J. D. Rolim, “A Comparative Study of Performance of AES Final Candidates Using FPGAs,” Proc. Cryptographic Hardware and Embedded Systems Workshop, CHES 2000, Worcester, MA, Aug 17–18, 2000.

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