A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA-Reference-Cited by-同舟云学术

A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA

Published:2000 Issue: Volume: Page:776-783
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Osmulski Timothy,Muehring Jeffrey T.,Veale Brian,West Jack M.,Li Hongping,Vanichayobon Sirirut,Ko Seok-Hyun,Antonio John K.,Dhall Sudarshan K.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-45591-4_107

Reference6 articles.

1. T. Osmulski, Implementation and Evaluation of a Power Prediction Model for Field Programmable Gate Array, Master’s Thesis, Computer Science, Texas Tech University, 1998.

2. K. P. Parker and E. J. McClusky, “Probabilistic Treatment of General Combinatorial Networks,” IEEE Trans. Computers, vol. C-24, pp. 668–670, June 1975.

3. B. Veale, Study of Power Consumption for High-Performance Reconfigurable Computing Architectures, Master’s Thesis, Computer Science, Texas Tech University, 1999.

4. T. L. Chou, K. Roy, and S. Prasad, “Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching,” Proc. IEEE Int’l Conf. Comput. Aided Design, pp. 300–303, Nov. 1994.

5. A. Nannarelli and T. Yang, “Low-Power Divider,” IEEE Trans. Computers, Vol. 48, No. 1, Jan. 1999, pp. 2–14.

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