Automatic Validation of Protocol Interfaces Described in VHDL

Author:

Corno Fulvio,Sonza Reorda Matteo,Squillero Giovanni

Publisher

Springer Berlin Heidelberg

Reference16 articles.

1. G. Al-Hayek, C. Robach: From Design Validation to Hardware Testing: A Unified Approach, JETTA: The Journal of Electronic Testing, Kluwer, No. 14, 1999, pp. 133–140

2. A.V. Aho, R. Sethi, J.D. Ullman, Compilers, Principles, Techniques, and Tools, Addison-Wesley Publishing Company, 1986

3. B. Beizer, Software Testing Techniques (2 nd ed.), Van Nostrand Rheinold, New York, 1990

4. F. Corno, P. Prinetto, M. Sonza Reorda: Testability analysis and ATPG on behavioral RT-level VHDL, Proc. IEEE International Test Conference, 1997, pp. 753–759

5. F. Corno, M. Sonza Reorda, G. Squillero, VEGA: A Verification Tool Based on Genetic Algorithms, Intl. Conf. on Circuit Design, 1998, pp. 321–326

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1. ARPIA: A High-Level Evolutionary Test Signal Generator;Lecture Notes in Computer Science;2001

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