Hardware Support for Multithreaded Execution of Loops with Limited Parallelism

Author:

Dimitriou Georgios,Polychronopoulos Constantine

Publisher

Springer Berlin Heidelberg

Reference32 articles.

1. Dimitriou, G., Polychronopoulos, C.: Loop Scheduling for Multithreaded Processors. In: IEEE Int. Conf. on Parallel Computing in Electrical Engineering, 2004, pp. 361–366 (2004)

2. Padua, D.A., Kuck, D.J., Lawrie, D.H.: High-speed Multiprocessors and Compilation Techniques. IEEE Trans. on Computers C-29(9), 763–776 (1980)

3. Polychronopoulos, C.D.: a-Coral: A New Multithreaded Processor Architecture, its Compiler Support, and Simulation of a multi-a-Coral Parallel System, Project Proposal, CSRD, University of Illinois at Urbana-Champaign (1997)

4. Smith, B.J.: A Pipelined, Shared Resource MIMD Computer. In: Int. Conf. on Parallel Processing, pp. 6–8 (1978)

5. Agarwal, A., Kubiatowicz, J., Kranz, D., et al.: Sparcle: An Evolutionary Processor Design for Multiprocessors. In: Int. Symp. on Microarchitecture, pp. 48–61 (1993)

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