1. R.A. Bergamaschi, S. Raje, Observable time windows: verifying high-level synthesis results. Design Test Comput. IEEE 14(2), 40–50 (1997). URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=587740&isnumber=12899
2. L.P. Carloni, K.L. McMillan, A. Saldanha, A.L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design. Comput. Aided Design 309–315 (1999). 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=810667&isnumber=17544
3. J. Cornet, F. Maraninchi, L. Maillet-Contoz, A method for the efficient development of timed and untimed transaction-level models of systems- on-chip. Design, Automation and Test in Europe, 2008. DATE ’08, pp. 9–14, 10–14 March 2008. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4484652&isnumber=4484624
4. E. Grimpe, F. Oppenheimer, Object-oriented high level synthesis based on SystemC. Electronics, Circuits and Systems, 2001. ICECS 2001.The 8th IEEE International Conference, 1, 529–534 (2001). URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=957798&isnumber=20704
5. E. Grimpe, F. Oppenheimer, Extending the SystemC synthesis subset by object-oriented features. Hardware/Software Codesign and System Synthesis, 2003. First IEEE/ACM/IFIP International Conference, pp. 25–30, 1–3 Oct. 2003. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1275251&isnumber=28532