A platform for combining deductive with algorithmic verification

Author:

Pnueli Amir,Shahar Elad

Publisher

Springer Berlin Heidelberg

Reference13 articles.

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2. E.M Clarke, O. Grumberg, H. Hiraishi, S. Jha, D.E. Long, K.L. McMillan, and L.A. Ness. Verification of the Futurebus+ cache coherence protocol. In L. Claesen, editor, Proc. of the 11th Int. Symp. on Computer Hardware Description Languages and their Applications. North-Holland, April 1993.

3. M. Gordon. Why higher-order logic is a good formalism for specifying and verifying hardware. In Formal Aspects of VLSI Design, pages 153–177. Elsevier Science Publishers (North Holland), 1986.

4. J.J Joyce and C.-J.H. Seger. Linking BDD-based symbolic evaluation to interactive theorem proving. In Proc. of the 30th Design Automation Conf., ACM, 1993.

5. R. Kurshan and L. Lamport. Verification of a multiplier: 64 bits and beyond. In C. Courcoubetis, editor, Proc. of 5th CAV, volume 697 of Lect. Notes in Comp. Sci., pages 166–179. Springer-Verlag, 1993.

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