Combining static worst-case timing analysis and program proof-Reference-Cited by-同舟云学术

Combining static worst-case timing analysis and program proof

Published:1996-09 Issue:2 Volume:11 Page:145-171
ISSN:0922-6443
Container-title:Real-Time Systems
language:en
Short-container-title:Real-Time Systems

Author:

Chapman Roderick,Burns Alan,Wellings Andy

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Control and Optimization,Computer Networks and Communications,Computer Science Applications,Modelling and Simulation,Control and Systems Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00365316.pdf

Reference49 articles.

1. Carré, B., and Garnsworthy, J. 1990. Experiences with SPARK and its support tool, the SPARK Examiner. Ada User 11 (Supplement):

2. Carré, B. A. 1990. Validation Techniques II. Software Engineering for Electronic System Designers. Peter Peregrinus Ltd. 248?255.

3. Carré, B. A., and Bergeretti, J. F. 1985. Information-flow and data-flow analysis of while-programs. ACM Transactions on Programming Languages and Systems 7: 37?61.

4. Carré, B. A., Jennings, T. J., Maclennan, F. J., Farrow, P. F., and Garnsworthy, J. R. 1992. SPARK: the SPADE Ada Kernel (edition 3.1). Program Validation Ltd.

5. Chapman, R. 1994. Worst-case timing analysis via finding longest paths in SPARK Ada basic-path graphs. Department of Computer Science, University of York.

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